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| $% SRAM FEATURES M21L216128A 128 K x 16 SRAM HIGH SPEED CMOS SRAM ORDERING INFORMATION 44-pin 400mil SOJ 44-pin 400mil TSOP (TypeII) Acess Time (ns) 10 T T T T T T T T T T Fast access times : 10, 12, and 15ns Fast OE access times : 5, 6, and 7ns Single +3.3V 0.3V power supply Fully static -- no clock or timing strobes necessary All inputs and outputs are TTL-compatible Three state outputs Center power and ground pins for greater noise immunity Easy memory expansive with CE and OE options Automatic CE power down +LJKSHUIRUPDQFH ORZSRZHU FRQVXPSWLRQ &026 WULSOHSRO\ GRXEOHPHWDO SURFHVV PRODUCT NO. M21L216128A-10J M21L216128A-10T M21L216128A-12J M21L216128A-12T M21L216128A-15J M21L216128A-15T PACKING TYPE SOJ TSOP 12 SOJ TSOP SOJ TSOP 15 GENERAL DESCRIPTION The M21L216128A is a high speed, low power asynchronous SRAM containing 2,097,152 bits and organized as 131,072 by 16 bits, it is produced by high performance CMOS process. This device offers center power and ground pins for improved performance and noise immunity. Static design eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, this device offers chip enable ( CE ), separate byte enable controls ( LB and HE ) and output enable ( OE ) with this organization. PIN ASSIGNMENT SOJ Top View A4 A3 A2 A1 A0 CE D Q1 D Q2 D Q3 DQ4 VCC GND DQ5 DQ6 DQ7 DQ8 WE A16 A15 A14 A13 A12 TSOP (TypeII) Top View A5 A6 A7 OE HB LB DQ 16 DQ 15 DQ 14 DQ 13 GND VC C DQ 12 DQ 11 DQ 10 D Q9 NC A8 A9 A10 A11 NC A4 A3 A2 A1 A0 CE D Q1 D Q2 D Q3 D Q4 VC C GND DQ5 DQ6 DQ7 DQ8 WE A1 6 A1 5 A1 4 A1 3 A1 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE HB LB DQ16 DQ15 DQ14 DQ13 GND VCC DQ12 DQ11 DQ10 D Q9 NC A8 A9 A1 0 A1 1 NC Elite Semiconduture Memory Technology Inc Publication Date : Sep. 2000 Revision : 1.0 1/14 $% Block Diagram eOO OA Uax M21L216128A 512 X 4096 xOOaxOa MEMORY ARRAY OAE xaA DQ9 Uaaec Oaeaa UAa Uaaec xOcO xOcO OUaOeUc OUaOeUc xaE xaAE OO O UO OUaOeUc aO eO Oaacaa Pin Descriptions Pin No. 1 - 5, 18 - 22, 24-27, 42 - 44 6 7 - 10, 13 - 16, 29 - 32, 35 - 38 17 39 40 Symbol A0 - A16 CE Description Address Inputs Chip Enable Input DQ1 - DQ16 WE LB HB Data Inputs/Outputs Write Enable Input Lower Byte Enable Input (DQ1 to DQ8) Higher Byte Enable Input (DQ9 to DQ16) Output Enable Input Power Ground No Connection 41 11, 33 12, 34 23, 28 OE VCC GND NC Elite Semiconduture Memory Technology Inc Publication Date : Sep. 2000 Revision : 1.0 2/14 $% ABSOLUTE MAXIMUM RATINGS * Voltage on VCC Supply Relative to Vss ... ......-0.5V to +4.6V VIN ......................................................-0.5V to VCC+1.0V Operating Temperature, Topr ....................... 0 C to +70 C Storage Temperature (plastic) ...................-55 C to +125 C Junction Temperature ..........................................+125 C Power Dissipation ...................................................1.0W Short Circuit Output Current ....................................50mA M21L216128A *Stresses greater than those listed under Absolute Maximum. Ratings may permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATIONS (All Temperature Ranges ; VCC = 3.3V 0.3V unless otherwise noted) DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage 0V VIN VCC Output(s) disable 0V VOUT VCC IOH = -4.0 mA IOL = 8.0 mA CONDITIONS SYMBOL VIH VII ILI ILO VOH VOL VCC 3.0 MIN 2.2 -0.5 -10 -5 2.4 0.4 3.6 MAX VCC+0.5 0.8 10 5 UNITS NOTES V V A A V V V 1 1 1 1,2 1,2 DESCRIPTION Power Supply Current : Operating TTL Standby CMOS Standby CONDITIONS Device selected; CE VIL; VCC=MAX; f=fMAX ; outputs open CE VIH; VCC=MAX; f=fMAX CE1 VCC-0.2; VCC = MAX; all other inputs GND +0.2 or VCC -0.2; all inputs static ; f=0 SYMBOL -10 ICC ISB1 ISB2 190 35 10 MAX -12 160 30 10 -15 130 25 10 UNITS mA mA mA NOTES 3 CAPACITANCE DESCRIPTION Input Capacitance Input/Output Capacitance(DQ) CONDITIONS TA= 25C ; f=1 MHz VCC=3.3V SYMBOL CI CI/O MAX 6 8 UNITS NOTES pF pF 4 4 Elite Semiconduture Memory Technology Inc Publication Date : Sep. 2000 Revision : 1.0 3/14 $% AC ELECTRICAL CHARACTERISTICS (Note 5)(All Temperature Ranges; VCC =3.3V 0.3V) DESCRIPTION Read Cycle Read Cycle Time Access access time Chip Enable access time Output hold from address change Chip Enable to output in Low-Z Chip disable to output in High-Z Output Enable access time Output Enable to output in Low-Z Output Disable to output in High-Z Byte Enable access time Byte Enable to output in Low-Z Byte disable to output in High-Z Write Cycle Write cycle time Chip Enable to end of write Address valid to end of write, with OE HIGH Address setup time Address hold from end of write Write pulse width Write pulse width, with OE HIGH Data setup time Data hold time Write disable to output in Low-Z Byte Enable to output in High-Z Byte Enable to end of write tWC tCW tAW tAS tWR tWP2 tWP1 tDW tDH tOW tWHZ tBW 8 10 8 8 0 0 10 8 5 0 3 5 8 12 8 8 0 0 10 8 6 0 4 6 9 15 9 9 0 0 11 9 7 0 5 tRC tAA tACE tOH tCLZ tCHZ tOE tOLZ tOHZ tBE tBLZ tBHZ 0 5 0 5 6 0 6 3 3 5 5 0 6 7 0 10 10 10 4 4 6 6 0 12 12 12 4 4 15 SYMBOL -10 MIN MAX MIN -12 MAX MIN M21L216128A -15 MAX UNIT Notes ns 15 15 ns ns ns ns 7 7 ns ns ns 7 8 ns ns ns 7 ns 4,7 4,6,7 4,6 4,7 4,6,7 ns ns ns ns ns ns ns ns ns ns 7 ns ns 4,7 4,6,7 Elite Semiconduture Memory Technology Inc Publication Date : Sep. 2000 Revision : 1.0 4/14 $% TRUTH TABLE MODE LOW BYTE READ (DQ1-DQ8) HIGH BYTE READ (DQ9-DQ16) WORD READ (DQ1-DQ16) LOW BYTE WRITE (DQ1-DQ8) HIGH BYTE WRITE (DQ9-DQ16) WORD WRITE (DQ1-DQ16) CE WE OE LE HE M21L216128A DQ1-DQ8 Q HIGH-Z Q D HIGH-Z D HIGH-Z HIGH-Z HIGH-Z DQ9-DQ16 HIGH-Z Q Q HIGH-Z D D HIGH-Z HIGH-Z HIGH-Z POWER ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE STANBY L L L L L L L H H H L L L X H X L L L X X X X H X L H L L H L H X X H L L H L L H X X OUTPUT DISABLE L STANDBY H AC TEST CONDITIONS Input plus levels Input rise and fail times Input timing reference levels Output reference levels Output load 0V to 3.0V 1.5ns 1.5V 1.5V See Figures 1 and 2 3.3V 317 DQ 30pF 351 DQ Z0 =50 e 50 Vt=1.5V e e e 5pF Fig.1 OUTPUT LOAD EQUIVALENT Fig.2 OUTPUT LOAD EQUIVALENT Elite Semiconduture Memory Technology Inc Publication Date : Sep. 2000 Revision : 1.0 5/14 $% NOTES 1. 2. All voltages referenced to GND (VSS). Overshoot : VIH +6.0V for t tRC /2. Undershoot : VIL -2.0V for t tRC /2. 3. 4. 5. 6. 7. 8. 9. M21L216128A ICC is given without output current. ICC increases with greater output loading and faster cycle times. This parameter is sampled. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. Output loading is specified with CL=5pF as in Fig.2. Transition is measured 500mV from steady static voltage. At any give temperature and voltage conditions, tCHZ is less than tCLZ and tWHZ is less than tOW WE is High for Read cycle. Device is continuously selected. Chip enable and output enables are held in their active state. 10. Address valid prior to, or coincident with, latest occurring chip enable. 11. tRC=Read Cycle Time. 12. Chip Enable and Write Enable can initiate and terminate a Write cycle. 13. Capacitance derating applies to capacitance different from the load capacitance shown in Fig. 1. Elite Semiconduture Memory Technology Inc Publication Date : Sep. 2000 Revision : 1.0 6/14 $% Timing Waveforms Read Cycle 1(8, 9) tRC Addr ess M21L216128A tAA tCH Dout Read Cycle 2(7, 8, 9, 10) tRC Addr es s tAA CE tACE tCLZ HB,LB tCHZ tBE tBLZ tBHZ OE tOE tOLZ Dout tOHZ : DON'T CARE : UNDEFINED Elite Semiconduture Memory Technology Inc Publication Date : Sep. 2000 Revision : 1.0 7/14 $% Timing Waveforms (continued) Write Cycle 1(7, 12, 13) (Write Enable Controlled with Output Enable OE active LOW) M21L216128A tWC Address tAW CE tWR tCW tBW HB,LB tA S tWP2 WE tDW Di n tDH tWHZ Dout tOW DON'T CARE U NDEFINED Elite Semiconduture Memory Technology Inc Publication Date : Sep. 2000 Revision : 1.0 8/14 $% Timing Waveforms (continued) Write Cycle 2(12, 13) (Write Enable Controlled with Output Enable OE active HIGH) M21L216128A tWC Address tAW CE tWR tCW tBW HB,LB tA S tWP1 WE tDW Di n tDH Dout HIG H-Z DON'T CARE U NDEFINED Elite Semiconduture Memory Technology Inc Publication Date : Sep. 2000 Revision : 1.0 9/14 $% Timing Waveforms (continued) Write Cycle 3(12, 13) (Chip Enable Controlled) M21L216128A tW C A d d res s tAW tAS CE tWR tCW tBW HB,LB tWP1 WE tDW Din tDH Dout HIGH -Z DON'T CARE UN DEFINED Elite Semiconduture Memory Technology Inc Publication Date : Sep. 2000 Revision : 1.0 10/14 $% Timing Waveforms (continued) Write Cycle 4(12, 13) (Byte Enable Controlled) M21L216128A tW C A d d res s tAW tCW CE tAS HB,LB tBW tWR tWP1 WE tDW Din tDH Dout HIGH -Z DON'T CARE UN DEFINED Elite Semiconduture Memory Technology Inc Publication Date : Sep. 2000 Revision : 1.0 11/14 $% PACKING 44-LEAD DIMENSIONS SOJ SRAM(400mil) M21L216128A SYMBOL A A1 A2 b b1 c c1 D E E1 DIMENSION ( INCH ) MIN 0.128 0.082 0.025 0.015 0.015 0.007 0.007 1.120 0.435 0.394 0 0.050BSC NOM 0.138 0.008 1.125 0.440 0.400 MAX 0.148 0.020 0.018 0.013 0.011 1.130 0.445 0.405 10 MIN 3.25 2.08 0.60 0.38 0.38 0.18 0.18 28.45 11.05 10.01 0 DIMENSION ( MM ) NOM 3.51 0.20 28.58 11.18 10.16 MAX 3.76 0.51 0.46 0.21 0.28 28.70 11.30 10.29 10 1.27 BSC e Elite Semiconduture Memory Technology Inc Publication Date : Sep. 2000 Revision : 1.0 12/14 $% PACKING 44-LEAD DIMENSIONS TSOP(II) SRAM(400mil) M21L216128A Symbol A A1 A2 B B1 C C1 D ZD E E1 L L1 e Dimension in mm Min Norm Max 1.20 0.05 0.15 0.95 1.00 1.05 0.30 0.45 0.30 0.35 0.40 0.12 0.21 0.10 0.16 18.28 18.41 18.54 0.805 REF 11.56 11.76 11.96 10.03 10.16 10.29 0.40 0.59 0.69 0.80 REF 0.80 BSC Dimension in inch Min Norm Max 0.047 0.002 0.006 0.037 0.039 0.042 0.012 0.018 0.012 0.014 0.016 0.005 0.008 0.004 0.006 0.720 0.725 0.730 0.0317 REF 0.455 0.463 0.471 0.395 0.400 0.4 0.016 0.023 0.027 0.031 REF 0.0315 BSC Elite Semiconduture Memory Technology Inc Publication Date : Sep. 2000 Revision : 1.0 13/14 $% ,PSRUWDQW 1RWLFH $OO ULJKWV UHVHUYHG M21L216128A 1R SDUW RI WKLV GRFXPHQW PD\ EH UHSURGXFHG RU GXSOLFDWHG LQ DQ\ IRUP RU E\ DQ\ PHDQV ZLWKRXW WKH SULRU SHUPLVVLRQ RI (607 7KH FRQWHQWV FRQWDLQHG LQ WKLV GRFXPHQW DUH EHOLHYHG IRU DQ\ WR EH DFFXUDWH LQ WKLV DW WKH WL PH RI SXEOLFDWLRQ UHVHUYHV QRWLFH WKH (607 ULJKW DVVX PHV FKDQJH QR WKH UHVSRQVL ELOLW\ SURG XFWV RU HUURU LQ GRFX PHQW DQG WR VSHFLILFDWLRQ WKLV GRFX PHQW ZLWKRXW 7KH LQIRUPDWLRQ RI RI FRQWDLQHG KHUHLQ 1R LV SUHVHQWHG RQO\ LV DV D JXLGH RU E\ H[DPSOHV (607 ULJKWV IRU WKH DQ\ DSSOLFDWLRQ RXU SURGXFWV UHVSRQVL ELOLW\ RU XVH RWKHU 1R DVVX PHG IRU RI LQIULQJHPHQW SDUWLHV ZKLFK LV SDWHQWV FRS\ULJKWV IUR P DQ\ LWV LQWHO OHFWXDO OLFHQVH SURSHUW\ WKLUG RU PD\ UHVXOW HLWKHU RU H[SUHVV LPSOLHG RWKHUZLVH JUDQWHG XQGHU SDWHQWV FRS\ ULJKWV RWKHU LQWHOOHFWXDO SUR SHUW\ ULJKWV RI (607 RU RWKHUV $Q\ VHPLFRQG XFWRU GHYLFHV PD\ KDYH LQKHUHQWO\ D FHUWDLQ UDWH RI IDLOXUH 7 R P LQL P L]H ULVNV DVVRFLDWHG ZLWK FXVWR PHU V DSSOLFDWLRQ DGHTXDWH GHVLJQ DQG RSHUDWLQJ VDIHJXDUGV DJDLQVW LQMXU\ GDPDJH RU ORVV IURP VXFK IDLOXUH VKRXOG EH SURY LGHG E\ WKH FXVWRPHU ZKHQ PDNLQJ DSSO LFDWLRQ GHVLJ QV (607 V OL PLWHG GLUHFWO\ SURGXFWV OLIH DUH QRW DXWKRUL]HG RU IRU XVH LQ FULWLFDO DSSOLFD WLRQV RU VXFK DV EXW QRW WR VXSSRUW KX PDQ GHYLFHV RU V\VWHP ZKHUH I DLOXUH RU DEQRUPDO RSHUDWLRQ ,I PD\ DIIHFW OLYHV FDXVH SK\VLFDO LQMXU\ SURSHUW\ GDPDJH SURGXFWV GHVFULEHG KHUH DUH WR EH XVHG IRU VXFK NLQGV RI DSSOLFDWLRQ SXUFKDVHU PXVW GR LWV RZQ TXDOLW\ DVVXUDQFH WHVWLQJ DSSURSULDWH WR VXFK DSSOLFDWLRQV Elite Semiconduture Memory Technology Inc Publication Date : Sep. 2000 Revision : 1.0 14/14 |
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